When accessing a range of indices (a slice) of a SystemVerilog array, you can specify a variable slice by using the and notations. SystemVerilog arrays support many more operations than their traditional Verilog counterparts. Mem_type ba // array of eight unpacked 'mem_type' elements Typedef bsix mem_type // array of four unpacked 'bsix' elements Typedef bit bsix // multiple packed dimensions with typedefīsix v5 // equivalent to bit v5 When an array has multiple dimensions that can be logically grouped, it is a good idea to use typedef to define the multidimensional array in stages to enhance readability.īit joe // 10 elements of 4 8-bit bytes Creating a multidimensional packed array is analogous to slicing up a continuous vector into multiple dimensions. Multidimensional arrays can be declared with both packed and unpacked dimensions. An array slice can only apply to one dimension other dimensions must have single index values in an expression. In SystemVerilog arrays, you can also select one or more contiguous elements of an array. Verilog arrays could only be accessed one element at a time. Indexing and Slicing SystemVerilog Arrays Each fixed-size dimension is represented by an address range, such as, or a single positive number to specify the size of a fixed-size unpacked array, such as. Unpacked arrays can be made of any data type. This also means you cannot have packed arrays of integer types with predefined widths (e.g. Packed arrays can be made of only the single bit data types ( bit, logic, reg), enumerated types, and other packed arrays and packed structures. A packed array is guaranteed to be represented as a contiguous set of bits in simulation and synthesis. Packed array divides a vector into subfields, which can be accessed as array elements. Int Array // unpacked array declaration using sizes Packed ArraysĪ one-dimensional packed array is also called a vector. Int Array // unpacked array declaration using ranges Unpacked array refers to the dimensions declared after the data identifier name.īit c1 // packed array of scalar bit Packed array refers to dimensions declared after the type and before the data identifier name. SystemVerilog arrays can be either packed or unpacked. In this article, we’ll take a look at the synthesizable features of SystemVerilog Arrays we can use when writing design RTL. In comparison, SystemVerilog arrays have greatly expanded capabilities both for writing synthesizable RTL, and for writing non-synthesizable test benches. In my last article on plain old Verilog Arrays, I discussed their very limited feature set.

$timeformat systemverilog